1. Field of the Invention
The present invention relates to a description processing device and a description processing method suitable for increasing parallelism by converting a behavior level description for designing an electronic circuit, and a recording medium recording program for realizing them on a computer.
2. Description of the Related Art
Because of advance in computer techniques, designing, analysis, evaluation, etc. of semiconductor integrated circuits has been commonly carried out by using a Computer-Aided Design (CAD) system having a behavioral synthesis tool and a logic synthesis tool. For example, Unexamined Japanese Patent Application KOKAI Publication No. 2007-272671 discloses a circuit design supporting system having a behavioral synthesis tool and a logic synthesis tool.
When a semiconductor integrated circuit is to be designed by using the circuit design supporting system, first, a designer prepares a behavior level description including the information necessary for hardware implementation of bit width, etc. of an input port and variables.
Next, by using the behavioral synthesis tool, the designer converts the behavior level description to a Register Transfer Level (RTL) description expressing the logics, which are to be implemented, by registers and logic functions between the registers. Then, the designer converts the RTL description to logic circuits of the gate level by using the logic synthesis tool.
In such design of an electronic circuit, techniques of increasing parallelism by speculatively calculating conditional expressions of conditional branching, THEN part, and ELSE part have been disclosed in, for example, Unexamined Japanese Patent Application KOKAI Publication No. H5-334391, Unexamined Japanese Patent Application KOKAI Publication No. H5-334466, and “Global Scheduling Independent of Control Dependencies based on Condition Vectors,” by Kazutoshi Wakabayashi and Hiroshi Tanaka, Proc. of 29th ACM/IEEE Design Automation Conference, pp 112 to 115, 1992, 6 (referred to as “Non-Patent Literature 1”).
Even when a label statement declaring a label which is a jump destination of a jump statement is present, there is a demand to constitute a high-speed electronic circuit by applying the techniques disclosed in Non-Patent Literature 1 and increasing parallelism by, for example, deleting or moving the label statement by parallelizing statements in the vicinity of the statement.